Integrated circuits (ICs) can be severely damaged by conducting discharge current of electrostatic charges through the circuits. Protection circuits are typically used to discharge the charges (which appear at input and/or output pads of the circuits), and are typically integrated into the ICs.
Designing protection circuitry involves providing efficient ESD discharging paths between all pad combinations. To achieve that effectiveness each pad requires typically dedicated protection circuitry.
Protection of input pads becomes very difficult in deep submicron complementary metal oxide silicon (CMOS) technologies. The problem comes from the fact that deep submicron processes use very thin oxides (thickness below 10 nm) with low breakdown voltages, below 10V. In order to serve as a useful protection device against an ESD event, its threshold voltage has to be lowered below the oxide breakdown voltage.
A typical circuit used for input pad ESD protection is shown in FIG. 1A. It consists of a grounded gate N-MOS transistor M1 having its drain terminal connected to the IC pad, its source and substrate to Vss and its gate to Vss. During normal IC operation the M1 transistor is off. The M1 transistor is a large geometry MOS transistor intended as the ESD discharge path between the protected pad and Vss terminal.
Under ESD stress condition, when the input pad is stressed negative in respect to the ground (Vss), the drain-substrate junction of the M1 transistor becomes forward biased and conducts the discharge current to the Vss. When the input pad is stressed positive in respect to the ground, the dominant current conduction path involves a parasitic bipolar transistor operating in the snapback region.
For ESD event in respect to Vdd, a p-channel MOS transistor M2 with its gate shorted to Vdd can be connected between the protected pad and Vdd, with its function similar to that of M1 transistor, as shown in FIG. 1B.
The snapback phenomenon in the MOS transistor involves the parasitic bipolar transistor action that takes place when its drain pin is stressed positive respect to ground as shown in FIGS. 2A and 2B, wherein FIG. 2A shows the breakdown and snapback and FIG. 2B shows the parasitic bipolar transistor in the IC involving the FET and its substrate. Increased current conduction in the snapback region is initiated by an avalanche breakdown of the drain-substrate junction of the M1 transistor that usually occurs in the 12V-15V range. This voltage is too high a voltage for most submicron CMOS technologies, in which the typical breakdown voltage of gate oxide is smaller than 12V-15V. Therefore it is important for effective ESD protection, to decrease the snapback voltage to a value lower than the breakdown voltage of the gate oxide.
Since grounded-gate multifinger N-channel MOS devices as shown in FIG. 1A are known to have a broad ESD failure-threshold distribution, an improved gate-coupled structure uses an additional transistor (M2 in FIG. 3) connected between the gate of the N-channel pull-down transistor M1 and the Vss pin. The M2 MOS transistor is a small NMOS transistor which is always on during normal circuit operation. Its function is to turn off the M1 transistor by discharging its gate to ground.
During a positive high voltage ESD pulse the gate of the M1 transistor is biased positively due to a capacitive divider created by transistors M1 and M2. Typical voltage at the FET M1 transistor gate is about 1V, the exact value depending on process conditions (gate-drain overlap capacitance) and transistor sizing. This voltage opens the M1 transistor for conduction during ESD transient and initiates snapback more easily as compared to the grounded gate case. It is widely recognized in practice that this solution provides more uniform finger switching than a grounded gate scheme.
Similar protection configuration can be applied for P-channel pull-up transistors for the case of high voltage ESD pulses with reference to the Vdd pin. However, effectiveness of this configuration is doubtful since PMOS (pnp) is difficult to be put in a snapback mode.
A more effective solution that has been proposed for ESD protection of input/output pads involves using a semiconductor controlled rectifier (SCR) with a low threshold voltage (typically 8V-12V) connected between the protected pad and the Vss. The problem with this low voltage SCR is that once turned on it can stay in the on state even when a triggering signal vanishes or that it can turn on during normal circuit operation.